In the semiconductor industry, there is a continuing trend toward higher device densities. To achieve these high densities, there has been and continues to be efforts toward scaling down device dimensions to submicron levels (e.g., below 0.35 microns) on semiconductor substrates. In order to accomplish such high device packing density, smaller and smaller features sizes are required. This may include the width and spacing of metal interconnecting lines, spacing and diameter of contact holes, and the surface geometry such as corners and edges of various features.
Single damascene is a technique developed to address disadvantages (e.g., poor metal step coverage, residual metal shorts, low yields, uncertain reliability, and poor ULSI integration extendability) associated with traditional etch back methods. Damascene basically involves the formation of a trench which is filled with a metal. Thus, damascene differs from traditional etch back methods which involve building up a metal wiring layer and filling the interwiring spaces with a dielectric material.
An improvement to single damascene is dual damascene which involves substantially simultaneous formation of a conductive via and conductive wiring. The dual damascene technique requires less manipulative steps than the single damascene technique and eliminates the interface between the conductive via and conductive wiring which is typically formed by the single damascene technique. In very and ultra large scale integration (VLSI and ULSI) circuits, an insulating or dielectric material, such as silicon oxide, of the semiconductor device in the dual damascene process is patterned with several thousand openings for the conductive lines and vias which are filled with metal, such as aluminum, and serve to interconnect active and/or passive elements of the integrated circuit.
In a via-first dual damascene process, vias are first anisotropically etched in a dielectric by conventional photolithographic and etching techniques. A second anistropically etched opening referred to as a trench line is then formed in the dielectric according to a second photolithographic patterning process overlying an encompassing the via opening. The via opening and the trench line together makeup the dual damascene structure which is subsequently filled with a conductive material (e.g., a metal).
During the formation of the trench line, a via fill material is employed to protect the bottom surface of the via. The via fill is employed as a stop material layer to protect the bottom surface of the via from further etching. The via fill is also employed as a planarizing layer for subsequent trench patterning. The via fill can be employed alone or in conjunction with a bottom anti-reflective coating (BARC) material layer. However, fences or ridges can form on the outer perimeter of the via caused by residual via fill material and/or BARC material during the etching of the trench line, since the dielectric material etches substantially faster (e.g., at least twice as fast) than the fill material and/or BARC material.
For example, FIG. 1 illustrates a dual damascene structure 10 at a stage in manufacturing formed by a via-first dual damascene process where a via opening 18 is formed in a dielectric layer 14 disposed over a substrate 12, followed by a formation of a trench opening 20 overlying and encompassing the via opening. Residual fences or etch ridges 22 remain around the outer periphery of the via opening 18 as a result the dielectric layer 14 etching substantially faster than a via fill material (not shown) and/or a BARC material layer 16. These ridges/fences 22 present serious yield/reliability issues, particularly in submicron processes.